The invention broadly relates to an electronic multi-level non-volatile memory device which is monolithically integrated in a semiconductor and incorporates a circuit structure for reading data contained in the memory.
In particular, the invention relates to a circuit structure for producing a current reference in a multi-level non-volatile memory, and the description which follows will cover this field of application just for convenience of explanation.
As is well known in this technical field, recent developments in the manufacture of non-volatile memories, specifically memories of the EPROM, EEPROM and FLASH types, point toward an increase of their storage capacity through the use of multi-level architectures, that is, memory matrices whose cells can store multiple logic states.
A preliminary comparative review of the circuit structures of conventional two-level memories may help, to make the aspects of this invention more clearly understood.
Electronic memory devices usually comprise at least one matrix of memory cells laid into rows and columns. Logic information can be written or read into/from each cell by suitably biasing a corresponding one of the rows or the columns.
A typical memory cell includes a field-effect transistor having a control gate terminal, a floating gate region, a source terminal, and a drain terminal. A potential range separates the two possible logic states of a two-level memory cellxe2x80x94e.g., a logic xe2x80x9c0xe2x80x9d to indicate a programmed cell, and a logic xe2x80x9c1xe2x80x9d to indicate an erased cell.
In operation, for the purpose of discriminating the informational contents of a two-level non-volatile memory cell, the memory cell is compared with a reference cell which is structurally identical to the memory cell but it doesn""t include program circuits.
The operation for selecting a memory cell in order to read its information contents consists in applying a suitable bias voltage to the control gate terminal of the cell. If the memory cell has been preliminarily programmed, then an electric charge is trapped within its floating gate region, and the threshold voltage of the cell is such that its current will be below that of the reference cell.
On the other hand, if the cell has been erased, no charge is trapped within its floating gate region, and the cell state can be identified by unbalanced-load comparison.
Thus, a method most frequently used for reading from a flash type of memory cell consists of comparing the current draw by the cell to be read and the current draw by the reference cell. A simple comparator, known as sense amplifier, is used to perform the comparison and output a corresponding result.
In the instance of a multi-level memory device, no less than 2nxe2x88x921 references are needed to discriminate a cell having an n-bit storage capacity, which references may be voltage- or current-oriented dependent on the reading method applied.
As an example, a prior method of determining the state of an n-level memory cell is described in U.S. Pat. No. 5,748,546, wherein the threshold voltage of a cell to be read is compared with a plurality (nxe2x88x921) of reference voltages From a structure standpoint, conventional two-level EPROMs have the reference cells and memory cells allocated to the same matrix. However, this solution may not be easily extended to multi-level memories because this would result in the area requirements increasing with the number of bits, and because the reference cells of a multi-level memory must be suitably programmed.
These difficulties are emphasized by the use of different reference cells for reading and programming. In fact, a reference line which included the as many reference cells as are the matrix cells could affect the reference cell read and/or program time to a significant extent.
An embodiment of this invention provides a circuit structure whereby the cell states of a preferably, but not exclusively, multi-level memory can be determined with only minor impact on the area requirements of the memory device and the reference cell reading speed.
The circuit structure provides, for each matrix block included in a specific read sector, a corresponding array which contains all the reference cells needed for comparison with the selected matrix cells.
Briefly, all the reference cells are placed in a sub-matrix which is associated with the memory cell matrix. Also, interconnecting paths are provided to maintain a true match of the matrix and the sub-matrix without affecting the reading access time.
The features and advantages of a circuit structure according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.